In electronic systems, good clock distribution can be very important to the overall performance of the product. Unwanted clock skew and jitter are two phenomena that may result from poor clock distribution, thus causing problems in the design and operation of the electronic system. Techniques have been developed using phase lock loops (PLLs) to successfully manage these problems and reduce both to manageable levels. However, current conventional solutions are not without some disadvantages.
Conventional PLL solutions can have certain advantages, including the fact that PLLs can suppress skew in digital systems (for example, clock to data out delay), can generate multiple phases of output clocks, and can be used to multiply or divide clock signals. In an exemplary application, a PLL may operate as a clock multiplier, where an input clock of 10 MHz may be multiplied by the PLL to yield 1000 Mhz. In an ideal embodiment, a clock multiplication function can result in an output CLK that is in perfect phase alignment with the input CLK.
A common implementation of a conventional PLL is that of a charge-pump based PLL. In this topology, a phase-frequency detector (PFD) is used to determine the relative phase and frequency of the PLL output and a reference clock input. The outputs of the PFD are coupled to a charge pump. The charge pump is used to add or subtract charge from a loop filter in response to PFD output signals by switching on or off electric currents of predetermined values for a duration determined by the PFD signals. The loop filter integrates charge from the charge pump, converting it to a voltage input to a voltage controlled oscillator (VCO). The VCO converts the voltage into the PLL output frequency. This output frequency can be connected back to the PFD input in some fashion.
Inputs received by a charge pump from a PFD can instruct a PLL to go “up” or “down” in frequency. These “up” and “down” signals have a duration that is proportional to the phase difference of the reference frequency and PLL output frequency, particularly when the two frequencies become very close. This phase difference is referred to as “phase error”. When a PLL is locked in both phase and frequency, this phase error is driven to a minimum that is determined by natural mismatches in the PFD, charge pump and other PLL circuitry, along with the precision with which the up and down signals are switched. This minimum phase error is referred to as static phase error.
To better understand various features of the disclosed embodiments, a conventional charge pump will be described with reference to FIG. 6. FIG. 6 shows a conventional complementary-metal-oxide-semiconductor (CMOS) charge pump 600, constructed of both n and p-type insulated gate field effect transistors (IGFETs). Charge pump 600 can include a pump up section 602, a pump down section 604, a “source” current source 606, and a “sink” current source 608. A pump up section 602 can include a first buffer 610, a p-type transistor P60, and n-type transistor N60. A pump up section 602 can receive an up input signal (UpM) that is applied to the input of first buffer 610 which has an output connected to the gate of a transistor P60. The up input signal (UpM) can also be applied to the gate of a transistor N60. Transistors P60 and N60 can form a stack from a higher power supply (VCC) to low power supply (VSS). A drain-drain connection of transistors P60 and N60 can form a node Node60 that is connected to source current source 606.
Referring still to FIG. 6, a pump down section 604 can include a second buffer 612, a p-type transistor P62, and n-type transistor N62. A pump down section 604 can receive a down input signal (Dn), where the down input signal is applied to the input of second buffer 612 which has an output connected to the gate of a transistor N62. The down input signal (Dn) can also be applied to the gate of transistor P62. Transistors P62 and N62 can form a second stack from a higher power supply (VCC) to a low power supply (VSS). A drain-drain connection of transistors P62 and N62 can form a node Node62 that is connected to sink current source 608.
Source current source 606 can source current (i.e., provide current) to an output node 614, while sink current source 608 can sink current (i.e., draw current) from output node 614, to thereby generate an output current lout.
Conventional charge pump 600 can operate in the following manner: When input signal Dn is high or input signal UpM is low, current flows either to or from output node 614. More particularly, current should only flow from output node 614 to ground (when signal Dn high) or from VCC to output node 614 (when signal UpM low). Current sources (606 and 608) can be a single transistor or several transistors (e.g., a cascade configuration). A buffer (610 or 612) may operate as a delay to improve transistor switching and minimize charge injection. The upper n-type transistor N60 and lower p-type transistor P62 can be present to effect a precise turn off of charge pump 600, which can minimize PLL static phase error.
Disadvantages of the conventional solution can include that when Dn is low and UpM is high, the charge pump is ideally off. However, in a conventional case like that of FIG. 6, when the charge pump is off, a small reverse current (shown as Irev(Up) and Irev(Dn)) can flow through either of the current sources (606 and 608) depending upon the implementation of the current sources. For example, current sources in a charge pump configured as current mirrors, can be referenced to bias transistors in another portion of a PLL circuit. More particularly, a current mirror can be a transistor whose gate is set, or biased, at a voltage that is between the lowest and highest voltages available in the charge pump. Because the current mirror device can be biased at a voltage that is not equal to the minimum or maximum voltage, under certain bias conditions a reverse current (Irev(Up) or Irev(Dn)) can arise, that flows in a direction opposite to the intended direction of the current source. A reverse current can become excessive as a voltage on output node 614 approaches high or low limits (i.e., VCC or VSS). Such a reverse current can cause ripples on output node 614 as a corresponding PFD/charge pump repeatedly updates the loop filter voltage and the reverse current alternately degrades the loop filter voltage. This ripple can lead to a time varying frequency at the output of the VCO. This time varying frequency is often referred to as long-term jitter. As noted above, as an output node 614 voltage reaches the voltage extremes available to the PLL, the reverse leakage increases in magnitude. This phenomenon can limit the useful range of the voltage on the loop filter (lout).
In addition, an unintended reverse current through current sources (such as biased current mirrors), can increase as the geometry of the devices used in such circuits decreases, as is the case in advanced manufacturing processes. This can be true even when the charge pump devices are operating in the sub-threshold region of operation. For smaller geometry devices, sub-threshold currents in the weak inversion region of operation are typically much higher. This can further reduce the usable range of loop filter voltage. Compounding this problem, small geometry processes must also be operated at lower voltage ranges in order to protect these small devices from overstress.